1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly but not exclusively to integrated circuit packaging.
2. Description of the Background Art
As is well known, an integrated circuit may be fabricated on a die on a semiconductor wafer. The semiconductor wafer may include several dies that are individually separated during a dicing process. Each die is then packaged to protect the die from environmental conditions and during handling, and to allow the die to be mounted on a printed circuit board or another substrate. In a typical packaging process, a lead frame is employed to support the die and to allow electrical connection to the die from the outside world. The lead frame consists of a die paddle on which the die is mounted and leads, which provide external electrical connections to the die. The leads may be electrically connected to the die by wire bonding, for example.
Some integrated circuits may be susceptible to erroneous electrical contact, electrostatic discharge (ESD) damage, or both. Unfortunately, currently available integrated circuit packages do not adequately address the need to protect an integrated circuit from erroneous electrical contact or ESD damage.